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NCP4302 Secondary Side Synchronous Flyback Controller
The NCP4302 is a full featured controller and driver that provide all the control and protection functions necessary for implementing a synchronous rectifier operation in a flyback converter. With the use of the NCP4302, the space conscious flyback applications such as Adaptors, chargers, set top boxes can achieve significant efficiency improvements at minimal extra cost. In addition to the synchronous rectifier control, the IC incorporates an accurate TL431 type shunt regulator, current monitoring circuit and optocoupler driver to provide a single IC secondary solution. The NCP4302 works with any type of flyback topology (continuous mode, Quasi-resonant mode or discontinuous mode) - providing a high level of versatility.
Features http://onsemi.com MARKING DIAGRAM
8 8 1 SO-8 D SUFFIX CASE 751 1 x A L Y W G = Reference Voltage (A or B) = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 4302x ALYW G
* Self-contained Control of Synchronous Rectifier in CCM, DCM, and * * * * * * * * * * * * * *
QR Flyback Applications Interface to External Signal for CCM Mode True Secondary Zero Current Detection High Gate Drive Currents (2.5 A Source/Sink) High Voltage Operation Current Sense Flexibility (MOSFET RDS(on) OR CS Resistor) Accurate Low Voltage Reference - NCP4302A 2.55 V, 1% - NCP4302B 1.275 V, 1% Programmable Independent Secondary Side ton and toff Delays Maximum Frequency of Operation up to 250 kHz These are Pb-Free Devices Notebook Adapters LCD TV Adapters Consumer Appliances such as DVD, VCR Power Over Ethernet Applications (IP phones, Wireless Access Points) Battery Chargers
PIN CONFIGURATION
SYNC/CS 1 TRIG 2 CATH 3 VREF 4 (Top View) 8 VCC 7 DRV 6 GND 5 DLYADJ
Typical Applications
ORDERING INFORMATION
Device NCP4302ADR2G Package SO-8 (Pb-Free) SO-8 (Pb-Free) Shipping 2500/Tape & Reel
NCP4302BDR2G
2500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2008
1
February, 2008 - Rev. 2
Publication Order Number: NCP4302/D
NCP4302
PIN DESCRIPTION
Pin Number 1 Symbol SYNC/CS Description Connected to the flyback winding. The current on this pin is sensed and used to turn on the Synchronous Rectification MOSFET (SRFET). This pin is also used to sense the zero crossing of the MOSFET current either using the RDS(on) of the SRFET or using an external current sense resistor connected between drain of the SRFET and the flyback winding. Input pin for direct turn-off of the MOSFET. Typically connected to a signal from primary controller (for CCM mode) or a signal derived from the transformer (for QR mode). Has very short propagation delay to output (<50 ns). Feedback compensation pin for the TL431 shunt regulator. Has the capability to sinking 10 ma of opto current. Output voltage feedback through resistive divider connected to this pin. Regulated at 1.28 V (option B) or 2.55 V (option A). A resistive divider between the power supply output and ground with the center point tied to the DLYADJ input pin allows for independent adjustment of the minimum ton and toff delay time. The maximum extern al capacitance from this pin to ground is 25 pF. Return pin for the controller - connected to the output return. Drive output for external MOSFET - 2.5 A peak drive capability, internally clamped to 13.5 V (Maxim um) Bias voltage for the controller. Maximum voltage is 28 V.
2
TRIG
3 4 5
CATH VREF DLYADJ
6 7 8
GND DRV VCC
MAXIMUM RATINGS
Rating Power Supply Input Current Drive Voltage Current Drive Current Source Sink Analog and Logic Inputs Maximum Voltage Current Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Reference input Current, continuous Total Power Dissipation Thermal Resistance Junction-to-Ambient Symbol VCC ICC VDRV IDRV 2.5 -2.5 TRIG, VREF, DLYADJ SYNC/CS TJ TJmax TSmax TLmax IREF PD qJA -0.3 to 10 100 - 10 to 95 100 -40 to 125 150 -65 to 150 300 -0.05 to 10 225 178 V mA V mA C C C C mA mW C/W Value -0.3 to 28 100 -0.3 to 18 100 Unit V mA V mA Apk
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pin 1-8: Human Body Model 2000 V per Mil-Std-883, Method 3015. Machine Model Method 200 V 2. This device contains Latch-up protection and exceeds 100 ma per JEDEC Standard JESD78
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NCP4302
VCC DRV GND
VCC Mngt. UVLO ON 10.4 V UVLO OFF 9.2 V UV CS in CS 95 V Dlyton ton and toff Comparators Dlyoff CS Out
30 V
VCC DRV
Reset Dominant SYNC/CS SQ RQ
CATH 30 V UV Idischarge DLYADJ ton and toff Ramp SQ RQ TL431 10 V VREF
Icharge
UV Cdelay 10 pF
10 V Charge Enable Discharge Enable TRIG 10 V
Figure 1. Block Diagram
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NCP4302
+VDC
Vout
+ J2
NCP1230 1 PFC_Vcc HV 2 FB 8 6 3 CS VCC 4 5 GND DRV
Vout
+
DRV Vcc SYNC/CS D LYADJ TRIG VREF GND CATH
Figure 2. Typical Application
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NCP4302
ELECTRICAL CHARACTERISTICS
(VCC = 19 V, Sync frequency = 100 kHz, VREF = VKA (IKA = 1 mA), RS = 75 ohms, VTRIG = GND, CDRV = 1 nF, RDLYADJ = 30.1 k, VDLYADJ = 2.0 V, for typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Rating VCC Start-up Threshold Stop Threshold VCC shutdown Hysteresis Supply current after turn-on Supply current after turn-on DRIVE OUTPUT Output voltage rise-time 10-90% of the output signal SYNC/ CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V 10-90% of the output signal SYNC/ CS = 0 to -0.5 V, 100 kHz, 5 ms pulse, Trig = 0 V tr 40 ns VCC , SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V VCC , SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V VCC(on) - VCC(off) no-load on DRV pin, SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V VCC(on) VCC(off) VCC(HYS) ICC1 ICC2 9.6 8.5 0.9 10.4 9.2 1.2 2.7 3.6 11.2 1.4 5.6 7.5 V V V mA mA Test Conditions Symbol Min Typ Max Unit
Output voltage fall-time
tf
-
-
40
ns
Output source current (Note 3) Driver high level output voltage ISOURCE = 200 mA, SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V, VCC = 12 V
IDRV(source) VDRV(H)
6.5
2.5 9.5
-
Apk V
Output sink current (Note 3) Driver Output low level output voltage Drive voltage internal clamp ISINK = 200 mA, SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V, VCC = 12 V VCC = 28 V, SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V, DRVpin = 10 kW VCC = VCC(off) + 200 mV, DRV pin = 10 kW + 1 nF, SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V
IDRV(sink) VDRV(L)
-
2.5 160
500
Apk mV
VDRV(CLMP)
-
-
17
V
Minimum drive output voltage
VDRV(MIN)
5.5
6.5
-
V
SYNC/CS The total propagation delay from SYNC/CS to the DRV output SYNC/CS = +0.5 V to -0.5 V 100 kHz, 5 ms pulse, (Trig = 0 V)(Refer to the Drive Output specifications for Tr 50% of the output signal VSYNC/CS < -30 mV tp1 70 135 ns
Zero Current Detection Current Sense Pin Offset Voltage at Zero Current Level (Note 3) SYNC/CS Leakage current
Is(zcd) VS(ZCD)
50 -30 -
230 -
450 10
mA mV mA
VSYNC/CS = 95 V
SCSLeakage
TRIGGER SECTION Minimum Trigger pulse duration 3. Guaranteed by Design SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig trig-pw 75 ns
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NCP4302
ELECTRICAL CHARACTERISTICS
(VCC = 19 V, Sync frequency = 100 kHz, VREF = VKA (IKA = 1 mA), RS = 75 ohms, VTRIG = GND, CDRV = 1 nF, RDLYADJ = 30.1 k, VDLYADJ = 2.0 V, for typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Rating TRIGGER SECTION Trigger Pulse Voltage for Gate turn-off Propagation delay from TRIG to DRV turn-off TL431 CHARACTERISTICS Reference input voltage IKA = 5 mA, VKA = VREF NCP4302A TJ = +25C TJ = -40C to +125C Reference input voltage (IK = 5 mA, VKA = VREF) NCP4302B TJ = +25C TJ = -40C to +125C IKA= 10 mA ISOURCE 0 to 1 mA DVKA = VCCon- 16 V, IKA = 1 mA VREF 1.262 1.249 IRef IKA VKA 1.275 0.0018 0.5 2.0 1.288 1.301 4.0 1.0 5.0 mA mA mV/V VREF V SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig CDRV = no-load, SYNC/CS= -0.5 V 100 kHz, 5 ms pulse, Trig = 0-5 V Vtrig tp2 2.0 25 4.0 85 V ns Test Conditions Symbol Min Typ Max Unit
2.525 2.499
2.55 -
2.575 2.60 V
Reference Input Current Minimum CATH current for regulation Reference voltage line regulation
+
Off-State CATH Current Dynamic impedance The maximum sink current capability ADJUSTABLE TIME DELAY The ton time delay
DV REF DV KA
IOff ZKA Isinkmax 10 11 0.62 20 1.5 mA W mA
VKA = 18 V, VREF = 0 V (test circuit 2, VREF pin grounded) VKA = VREF, DIKA = 1 mA to 10 mA (ISOURCE 0 to 10 mA)
SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V CDLYADJ internal = 10 pF (Vs = 2.0 V, Rth = 30.1 kW) * R2 = 190 kW, R3 = 57 kW * R2 = 499 kW, R3 = 39 kW (*See Figure 27) The maximum capacitance from pin 5 to ground is 25 pF.
ton(delay)
1.0
1.4
1.8
ms
The min and max ton(delay) range (Note 3) The maximum and minimum input voltage operating range. (Note 3) The maximum and minimum input operating current into the DLYADJ pin (Note 3) The toff time delay
ton(range) 0.45 VinDLYADJ 1.5 2.0 4.5
ms
V
IinDLYADJ
9
-
200
mA
SYNC/CS = 0 to -0.5 V 100 kHz, 5 ms pulse, Trig = 0 V CDLYADJ internal = 10 pF (Vs = 2.0 V, Rth = 30.1 k) R2 = 66 k, R3 = 23.6 k * R2 = 408 k, R3 = 32.4 k (*See the schematic below)
toff(delay)
3.1
4.1
5.1
ms
The min and max toff(delay) range (Note 3) 3. Guaranteed by Design
toff(range) 0.8 4.6
ms
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NCP4302
TYPICAL CHARACTERISTICS
10.6 VCC(on), VOLTAGE THRESHOLD (V) VTRIG = 0 V 10.5 VCC(off), VOLTAGE THRESHOLD (V) 9.4 VTRIG = 0 V 9.3
10.4
9.2
10.3
9.1
10.2 -50
-25
0
25
50
75
100
125
150
9.0 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 1. VCC(on) Threshold vs. Junction Temperature
VCC(HYS), SHUTDOWN HYSTERESIS (V) 1.40 ICC1, SUPPLY CURRENT (mA) 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -50 -25 0 25 50 75 100 125 150 VTRIG = 0 V 3.10
Figure 2. VCC(off) vs. Junction Temperature
VCC = 19 V 2.70 CDRV = No Load
2.30
1.90
1.50 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. VCC(HYS) vs. Junction Temperature
trise, OUTPUT VOLTAGE RISE TIME (ns) 4.40 ICC2, SUPPLY CURRENT (mA) VCC = 19 V 4.00 CDRV = 1 nF 3.60 35.0 30.0 25.0 20.0 15.0 10.0 5.0
Figure 4. Internal Current Consumption at No Load vs. Junction Temperature
CDRV = 1 nF
3.20
2.80
2.40 -50
-25
0
25
50
75
100
125
150
0 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. Supply Current Consumption with 1 nF Load vs. Junction Temperature
Figure 6. Drive Output Rise Time vs. Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
tfall, OUTPUT VOLTAGE FALL TIME (ns) 25.0 VDRV(H), DRIVER OUTPUT HIGH VOLTAGE (V) 150 CDRV = 1 nF 20.0 10.5
10.0
15.0
9.5
10.0
9.0
5.0
8.5
0 -50
-25
0
25
50
75
100
125
8.0 -50
0
50
100
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Drive Output Fall-time vs. Junction Temperature
VDRV(L), DRIVER OUTPUT LOW VOLTAGE (V) 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 -50 -25 0 25 50 75 100 125 150 VDRV(clmp), DRIVE VOLTAGE INTERNAL CLAMP (V) 14 12 10 8 6 4 2 0 -50
Figure 8. Driver Vout High vs. Junction Temperature
VCC = 28 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C) VDRV(min), MINIMUM DRIVE OUTPUT VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Driver Vout Low vs. Junction Temperature
10 9.0 8.0 7.0 6.0 5.0 4.0 -50 VCC = VCC(off) + 200 mV Load = 10 kW + 1 nF tp1, PROPAGATION DELAY FROM SYNC TO DRIVE OUTPUT (ns) 90 85 80 75 70 65 60 55 50 -50
Figure 10. Vgate Clamp vs. Junction Temperature
Cload = 1 nF
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. VOUT(min) vs. Junction Temperature
Figure 12. tp1 Propagation Delay, SYNC/CS to DRIVE vs. Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
300 IS(zcd), ZERO CURRENT DETECTION CURRENT (mA) VTRIG, TRIGGER PULSE VOLTAGE FOR GATE TURN-OFF (V) 3.2
250
3.1
200
150
3.0
100
2.9
50 -50
-25
0
25
50
75
100
125
150
-50 2.8
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Zero Current Detect Isource vs. Junction Temperature
90
tp2, PROPAGATION DELAY FROM TRIG TO DRV TURN-OFF(ns) 2.60 VREF, REFERENCE VOLTAGE (V)
Figure 14. Trigger Pulse Voltage for Gate Turn-off vs. Junction Temperature
Isource = 5 mA 2.55
80 70 60 50 40 30 20 -50 -25 0 25 50 75 100 125
2.50
2.45
150
2.40 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 15. tp2 Propagation Delay TRIG in to DRIVE Off, NO Load vs. Junction Temperature
IREF, REFERENCE INPUT CURRENT (nA) 40 35 30 25 20 15 10 5.0 0 -50 -25 0 25 50 75 100 125 IKA, MINIMUM CATH CURRENT FOR REGULATION (mA) 170
Figure 16. 2.55 V Reference (Option A) Voltage vs. Junction Temperature
160
150
140
130
150
120 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 17. 2.55 V Reference Input Current vs. Junction Temperature
Figure 18. 2.55 V Reference Minimum Cathode Current for Regulation vs. Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
Ioff, OFF-STATE CATH CURRENT (mA) -25 0 25 50 75 100 125 150 3.2 VKA, REFERENCE VOLTAGE LINE REGULATION (mV/V) 3 2.8 2.6 2.4 2.2 2 1.8 1.6 -50 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 19. 2.55 V Reference Line Regulation vs. Junction Temperature
1000 ZKA, DYNAMIC IMPEDANCE (mW) 900 800 700 600 500 400 300 -50 VREF, REFERENCE VOLTAGE (V) 1.28
Figure 20. 2.55 V Reference Off-State Cathode Current vs. Junction Temperature
Isource = 5 mA 1.27 1.26 1.25 1.24 1.23 1.22 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 21. 2.55 V Reference Dynamic Impedance vs. Junction Temperature
1.55 ton(delay), ON TIME DELAY (ms) 1.50 1.45 1.40 1.35 1.30 1.25 -50 5.5
Figure 22. 1.275 V Reference Voltage (Option B) vs. Junction Temperature
toff, OFF TIME DELAY (ms) -25 0 25 50 75 100 125 150
5
4.5
4
3.5
3 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 23. ton Delay vs. Junction Temperature
Figure 24. toff Delay vs. Junction Temperature
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NCP4302
Detailed Operating Description SYNC/CS Input
The NCP4302 is designed to operate either as a standalone IC or as a companion IC to a primary side controller to help achieve efficient synchronous rectification for flyback converter systems. It has high current gate driver along with fast logic circuitry to provide appropriately timed drive signals to a synchronous MOSFET used for output rectification in a flyback converter. With its novel architecture, the NCP4302 has enough versatility to increase the synchronous rectification efficiency under any operating mode without requiring too much complexity.
Supply Section
The NCP4302 works from an available bias supply that can range from 10.4 V to 28 V (typical). This allows direct connection to the output voltage of many adapters such as notebook and LCD TV adapters. As a result, the NCP4302 simplifies circuit operation compared to other devices which require specific bias power supplies (e.g. 5 V). The high voltage capability of the VCC is also a unique feature designed to allow operation across a broader range of applications. To prevent gate signal from operating under inadequate bias conditions, the NCP4302 features a UVLO circuit that turns on at 10.4 V (VCC rising) typical and turns off at 9.2 V typical (VCC falling).
Gate Drive Section
In a synchronous rectification application after the primary side MOSFET is turned-off, the current in the secondary of the flyback transformer initially flows through the synchronous rectification MOSFET's internal body diode. When this occurs, the drain of the MOSFET will be -0.5 to -1.0 V negative with respect to ground (the VF of the internal body diode) and the NCP4302 current sense differential amplifier will output a 230 mA current (typical). This current detection method is used by the NCP4302 to determine when current is flowing in the secondary of the transformer and the Synchronous Rectification MOSFET needs to be turned-on. The zero current detection senses the current with a slight negative offset so that the switch turn-off occurs without reversal of the current.
Cout
Vout
Current Sense Amplifier Mirror 75 To Reset Dominant Flip-Flop
The NCP4302 features high current gate drivers delivering up to (>2.5 A peak) to achieve fast turn-on and turn-off requirements in a synchronous rectifier. Having a high gate drive current enables fast turn-on when SYNC/CS signal is received (to minimize body diode conduction at the peak of the current waveform) and fast turn-off when zero current or a TRIG signals are received (to prevent current reversal or cross conduction). The higher sink current also allows the MOSFET to be kept off during the instances when there is high dv/dt on the drain. The gate voltage is clamped at 13.5 V typical to prevent larger excursion of gate voltage than needed when VCC is operating from a 28 Vdc output. The propagation delays through the logic circuits and the gate drivers are kept at a minimum as shown in the specification table.
45.0 V SYNCHRONOUS MOSFET DRAIN VOLTAGE (V) 37.5 V
Figure 25. Input Current Sense Adjustable ton Delay
The SYNC/CS input to the NCP4302 is used as a Reset (through logic) input to the drive enable Flip Flop; refer to the internal block diagram of the NCP4302. When current flows in the secondary of the Flyback transformer any parasitic inductance due to printed wiring board traces, or component lead can cause the voltage at the SYNC/CS input to ring above ground (refer to Figure 26). This ringing may cause the controller dive output to turn-off. To eliminate this problem the NCP4302 has a programmable ton time which blanks the secondary voltage ringing by adding a minimum controller drive on time.
25.0 V
12.5 V 0V
V(U1:4)
60 ms
70 ms
80 ms
90 ms
100 ms
110 ms
120 ms
Time
Figure 26. Discontinuous Conduction Mode Drain Waveform http://onsemi.com
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NCP4302
The minimum on time is set with a voltage divider with resistors R2 and R3 (refer to Figure 27).
I in + V out @ R3 * 0.7 @ 1 R3 ) R2 Rth Adjustable toff Delay
Where Rth is the Thevenin equivalent resistance and is calculated by:
Rth +
1 R3
1 1 ) R2
This input current is then used to charge an internal 10 pF capacitor setting the minimum ton time.
t on(delay) + 10 pF @ 4 V I in
Vout + Cout Rlower R3 R2 Rupper
The SYNC/CS input to the NCP4302 is used as the Set input to the drive enable Flip Flop; refer to the internal block diagram of the NCP4302. Refering to the SPICE simulations (Figure 28), you can see that when the system is operating under light load conditions the transformer secondary voltage rings below ground when the current reaches zero. When this occurs, the CS amplifier output may be falsely triggered providing a Set input to the Drive Flip Flop, turning on the output drive. To prevent the controller from prematurely turning on the synchronous rectification MOSFET, the output of the current sense amplifier is connected to a logic block with a programmable off time delay. The toff(delay) can be independently programmed through the DLYADJ pin.
I in + V out @ R3 R3 ) R2 * 0.7 @ 1 100k
t off(delay) + 10 pF @ 3.35 V I in
RS DRV VCC D SYNC/CS TRIG GND
LYADJ
Iin
VREF CATH
Figure 27. Typical Application
100 V SYNCHRONOUS MOSFET DRAIN VOLTAGE (V)
50 V
0V
-50 V 100 ms V(U1:4) 110 ms 120 ms 130 ms Time 140 ms 150 ms 160 ms
Figure 28. Discontinuous Conduction Mode Drain Waveform Trigger Input
The TRIG input is used to turn-off the synchronous MOSFET prior to its current reaching zero. This input is required in a CCM operating mode. While there are several ways to determine the TRIG input, the simplest way is to generate a pulse in the primary side that precedes the turn-on of the primary MOSFET and transformer couple that pulse to the secondary into the Trig input. In converters where the operating mode is always designed to be DCM or QRM, the
TRIG input is not used. It is recommended to ground the TRIG pin in these cases.
Voltage Amplifier and Reference
The NCP4302 incorporates an accurate TL431 type Shunt regulator with two reference voltage options. The NCP4302A has a 2.5 V reference and the NCP4302B has a 1.25 V reference.
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NCP4302
TX1 Cout Rbias
operate in CCM, CRM, or QR modes. The next sections cover the losses associated for each of the three operating modes.
Discontinuous Conduction Mode
Rupper
Rcomp Ccomp
TL431 Rlower
Figure 29. Typical Secondary Side Regulator
When the TL431 is being used to regulate the output of a power supply it is typically configured as shown in Figure 29. Where the output from the power supply is sensed and divided down with a resistive divider made up of Rupper and Rlower. The center point of the divider is connected to the reference pin of the NCP4302. The divider ratio scales down the output voltage to match the reference voltage, 2.5 V or 1.25 V.
V REF + V out @ R lower R lower ) R upper
The basic switching waveforms for the Flyback converter operating in DCM are shown in Figure 31. When the primary side MOSFET (SP in Figure 30) is turned-on current flows is the transformer primary and ramps up from zero to Ipeak. When the primary side MOSFET (SP) turns-off, the polarity of the transformer reverses and the energy stored in the transformer is transferred to the secondary. When the energy transfer from the transformer primary to the transformer secondary begins, (prior to the secondary side synchronous MOSFET turning-on) the secondary current flows through the internal body diode synchronous rectifiers MOSFETs (SS) and (SSD). To minimize the losses in the SSD, the propagation delay (tp1) must be low. Otherwise, there will be high losses associated with the secondary peak current and the SSD forward voltage drop (NCP4302 has a typical propagation delay of 50 ns).
P Tsecondary + P on ) P SW ) P diode I out + Isec,pk 2 @ (1 * D on) 1 * D on 3
(eq. 1)
(eq. 2)
The Rbias resistor in Figure 29 sets the current through the TL431, which must be greater than 0.5 mA to guarantee its performance under all operating conditions.
Vin Cout SSD Vout
I sec,rms + I sec,pk @
(eq. 3)
Combining equations 2 and 3,
I sec,rms 2 + P on + 4 @ I out 2 3 @ (1 * D on)
(eq. 4)
4 @ I out 2 @ R DS(on) 3 @ (1 * D on)
(eq. 5) (eq. 6) (eq. 7)
P SW + 1 @ C OSS @ V S 2 @ f 2
SP SS
P diode + V F @ Iout @ t delay
Figure 30. Synchronous Rectifier Using Synchronous Rectification
Where: Iout is the dc output current VF is D is the duty cycle RDS(on) is the on resistance of the MOSFET
V in V S + n ) V out
For a flyback converter to operate correctly with synchronous rectification there must be a delay between the time when the primary side MOSFET (SP Figure 30) and the secondary side Synchronous rectification MOSFETs (SS Figure 29) are conducting current. The NCP4302 can
n is the transformer turns ratio Tdelay is the delay from the sync to the drive output
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NCP4302
Discontinuous Condition Mode
SP DRV SP DRV Ipk Ipeak Ivally
Body-Diode Conduction Time ISEC
ISEC
SYNC DRV
SYNC DRV
tdelay1 tp1
Figure 31. Discontinuous Conduction Mode Waveforms
TRIG
tp1 is the propagation delay from the SYNC/CS input to the drive output.
Continuous Conduction Mode
Figure 32. Continuous Conduction Mode Waveforms P sync + P ON ) P Qrr ) P dP ) PPOFF
(eq. 8)
When operating in continuous conduction mode (CCM) the current in the secondary doesn't fall to zero prior to turning on the primary side MOSFET. To eliminate cross conduction losses (have the primary side MOSFET and secondary side MOSFET on at the same time) the trigger input to the NCP4302 must be utilized. A signal which leads the Primary Side (SP) MOSFET turning on must be coupled to the TRIG input of the NCP4302 which will turn-off the SS MOSFET referring to Figure 32. When the energy transfer begins in the transformer secondary, prior to the secondary side synchronous MOSFET turning-on, the secondary current flows through the synchronous rectifiers MOSFET's (SS) internal body diode (SSD). To minimize the power loss in the internal body the controller propagation delay has been minimized in the NCP4302.
I sec,RMS [
I sec,peak *
DI L
sec
2 DI L
I sec,RMS [
2
I sec,peak *
sec
2
Combining equations 9 and 10,
DIL sec + V OUT ) V f
LM n2
P on + I sec,RMS 2 @ R DS(on) P QRR + Q RR V OUT ) V IN n f
P BODY_DIODE + V f @ I OUT @ f(t delay1 ) td delay2) V in P off + 1 @ C OSS V out ) n 2
2
QRR is the recovery charge of the internal body diode Coss is the MOSFET drain to source capacitance LM is the transformer primary inductance
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EE EE EE EE EE
tdelay2
EE EE EE EE EE EE
EE EE EE EE EE
IPRM ISEC,PK
Ipeak,sec
Body-Diode Conduction Time
1*D
(eq. 9)
2
1*D
(eq. 10)
(1 * D)T
(eq. 11)
(eq. 12) (eq. 13) (eq. 14)
@f
(eq. 15)
NCP4302
ILSEC ISEC,PK IL
IOUT
Figure 33.
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NCP4302
PACKAGE DIMENSIONS
SOIC-8 NB SUFFIX CASE 751-07 ISSUE AH
-XA
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-YG C -ZH D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004) M ZY
S
J
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
The product described herein (NCP4302), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NCP4302/D

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